期末考

module top;
system_clock #400 clock1(a);
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #50 clock1(d);
number n1(e,a,b,c,d);
endmodule
module number(e1,a,b,c,d);
input a,b,c,d;
output e1;
wire a1,b1,c1,d1,w1,w2,w3,w4,w5,h1,h2,h3,h4,h5,g1,g2,g3,g4,g5;
nand(a1,a,a);
nand(b1,b,b);
nand(c1,c,c);
nand(d1,d,d);
nand(h1,b,c1,d1);
nand(w1,h1,h1);
nand(h2,a,c1,d1);
nand(w2,h2,h2);
nand(h3,c1,d);
nand(w3,h3,h3);
nand(h4,a1,b1,c,d1);
nand(w4,h4,h4);
nand(h5,a,b,d);
nand(w5,h5,h5);
nand(g1,w1,w1);
nand(g2,w2,w2);
nand(g3,w3,w3);
nand(g4,w4,w4);
nand(g5,w5,w5);
nand(e1,g1,g2,g3,g4,g5);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

NOT,AND,OR to NAND

把設計好的邏輯閘 NOT,AND,OR改成同一的邏輯閘NAND

module top;
system_clock #400 clock1(a);
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #50 clock1(d);
number n1(e,a,b,c,d);
endmodule
module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4,w5;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(w1,a1,b,c1);
and(w2,a,c1,d1);
and(w3,a,b,d1);
and(w4,a,b1,c,d);
and(w5,a1,b1,c,d1);
or(e,w1,w2,w3,w4,w5);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule