期末考

module top;
system_clock #400 clock1(a);
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #50 clock1(d);
number n1(e,a,b,c,d);
endmodule
module number(e1,a,b,c,d);
input a,b,c,d;
output e1;
wire a1,b1,c1,d1,w1,w2,w3,w4,w5,h1,h2,h3,h4,h5,g1,g2,g3,g4,g5;
nand(a1,a,a);
nand(b1,b,b);
nand(c1,c,c);
nand(d1,d,d);
nand(h1,b,c1,d1);
nand(w1,h1,h1);
nand(h2,a,c1,d1);
nand(w2,h2,h2);
nand(h3,c1,d);
nand(w3,h3,h3);
nand(h4,a1,b1,c,d1);
nand(w4,h4,h4);
nand(h5,a,b,d);
nand(w5,h5,h5);
nand(g1,w1,w1);
nand(g2,w2,w2);
nand(g3,w3,w3);
nand(g4,w4,w4);
nand(g5,w5,w5);
nand(e1,g1,g2,g3,g4,g5);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

NOT,AND,OR to NAND

把設計好的邏輯閘 NOT,AND,OR改成同一的邏輯閘NAND

module top;
system_clock #400 clock1(a);
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #50 clock1(d);
number n1(e,a,b,c,d);
endmodule
module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4,w5;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(w1,a1,b,c1);
and(w2,a,c1,d1);
and(w3,a,b,d1);
and(w4,a,b1,c,d);
and(w5,a1,b1,c,d1);
or(e,w1,w2,w3,w4,w5);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

加法器(input:Cin,A,B;output:Cout,Sum)邏輯電路

縮短模組( assign sum;assign carry_out)

module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = a^b^carry_in;
  assign carry_out = a^b|carry_in|a|b;
endmodule

加法器(input:Cin,A,B;output:Cout,Sum)卡諾圖

Cout: F1+ F2+ F3 = AB+CinA+CinB
Sum:(~a+b+~Cin)|(~Cin+a+~b)|(a+b+Cin)|(~a+~b+Cin)





module test_adder1;

 reg a,b;
 reg carry_in ;
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in)

 initial
  begin

    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 0+1+0=01 sum is WRONG!");
              else
               $display(" 0+1+0=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 1;
    # 100 if ( carry_out !== 1 | sum !== 1)
               $display(" 0+1+1=10 sum is WRONG!");
              else
               $display(" 0+1+1=10 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 0)
               $display(" 1+0+0=01 sum is WRONG!");
              else
               $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_out !== 0 | sum !== 1)
                $display(" 1+0+1=10 sum is WRONG!");
              else
                $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out !== 1 | sum !== 0)
               $display(" 1+1+0=10 sum is WRONG!");
              else
               $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_out !== 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");

    $finish;
  end
endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
  assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule

三位元多工器 行為模式設計 之參考範例

odule top;
  integer ia0,ia1,ia2,ib0,ib1,ib2,is;
  reg  a0,a1,a2,b0,b1,b2,s;
  wire out1,out2,out3;

  mux_behavioral mux1(out1,out2,out3,a0,a1,a2,b0,b1,b2,s);

  initial
    begin
      for (ia0=0; ia0<=1; ia0 = ia0+1)
        begin
          a0 = ia0;
          for (ia1=0; ia1<=1; ia1 = ia1+ 1)
            begin
              a1 = ia1;
                for (ia2=0; ia2<=1; ia2 = ia2+1)
                  begin
                    a2 = ia2;

                     for (ib0=0; ib0<=1; ib0 = ib0+1)
                       begin
                         b0 = ib0;
                          for (ib1=0; ib1<=1; ib1 = ib1+ 1)
                            begin
                              b1 = ib1;
                               for (ib2=0; ib2<=1; ib2 = ib2+ 1)
                                 begin
                                   b2 = ib2;

                                 for (is=0; is<=1; is = is + 1)
                                   begin
                                     s = is;
                 #20$display("a0=%d a1=%d a2=%d b0=%d b1=%d b2=%d s=%d out1=%d out2=%d out3=%d",a0,a1,a2,b0,b1,b2,s,out1,out2,out3);
                               end
                           end
                       end
                    end
                  end
              end
         end
   end
endmodule

module mux_behavioral(OUT1,OUT2,OUT3,A0,A1,A2,B0,B1,B2,SEL);
 output OUT1,OUT2,OUT3;
 input A0,A1,A2,B0,B1,B2,SEL;
 wire  A0,A1,A2,B0,B1,B2,SEL;
 reg   OUT1,OUT2,OUT3;

always @(A0 or A1 or A2 or B0 or B1 or B2 or SEL)
 begin
   OUT1 = (A0 & SEL)|(B0 & ~SEL );
   OUT2 = (A1 & SEL)|(B1 & ~SEL );
   OUT3 = (A2 & SEL)|(B2 & ~SEL );
 end
endmodule

三位元多工器 結構模式設計

設計得不好!!很亂

經過同學的教學 懂得怎樣設計~

module top; 

wire [2:0]A, B, OUT;

wire SEL;

system_clock #3200 clock1(A[0]);

system_clock #1600 clock2(A[1]); 

system_clock #800  clock3(A[2]); 

system_clock #400  clock4(B[0]); 

system_clock #200  clock5(B[1]); 

system_clock #100  clock6(B[2]);  

system_clock #50   clock7(SEL);  

mux3 mi(OUT, A, B, SEL);

endmodule

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL);

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module mux2(OUT, A, B, SEL);

output [1:0] OUT;

input [1:0] A,B;

input SEL;

mux hi (OUT[1], A[1], B[1], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

module mux3(OUT, A, B, SEL);

output [2:0] OUT;

input [2:0] A,B;

input SEL;

mux hi (OUT[1], A[1], B[1], SEL);

mux middle(OUT[2], A[2], B[2], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

二位元多工器 行為模式

module top; 

wire A0,A1,B0,B1,OUT1,OUT2;

wire SEL;

system_clock #50 clock1(SEL); 

system_clock #100 clock2(A0);

system_clock #200 clock3(A1);

system_clock #400 clock4(B0);

system_clock #800 clock5(B1);

mux_behavioral mux1 (OUT1,OUT2,A0,A1,B0,B1,SEL);

endmodule 

module mux_behavioral(OUT1,OUT2,A0,A1,B0,B1,SEL);

 output OUT1,OUT2;

 input A0,A1,B0,B1,SEL;

 wire  A0,A1,B0,B1,SEL;

 reg   OUT1,OUT2;

always @(A0 or A1 or B0 or B1 or SEL)

 begin

   OUT1 = (A0 & SEL)|(B0 & ~SEL );

   OUT2 = (A1 & SEL)|(B1 & ~SEL );

 end

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

練習邏輯閘

and_gate

or_gate

not_gate

上課練習邏輯閘

Binary bit-wise operators

– ~：NOT

– &：AND

– |：OR

– ^ ：XOR

– ~^,^~：XNOR

上課作品:二位元多工器

上課作品:二位元多工器

太多out，有點混亂..............

上課作品 一位元多工器

新體驗 : AND 5IN 1OUT 設計

運用3輸入的AND完成                                         2014.09.30

新體驗 : AND 3IN 1OUT 設計

運用2輸入的AND完成                                                                       2014.09.30

Verilog HDL!!!!