module top;
wire A0,A1,B0,B1,OUT1,OUT2;
wire SEL;
system_clock #50 clock1(SEL);
system_clock #100 clock2(A0);
system_clock #200 clock3(A1);
system_clock #400 clock4(B0);
system_clock #800 clock5(B1);
mux_behavioral mux1 (OUT1,OUT2,A0,A1,B0,B1,SEL);
endmodule
module mux_behavioral(OUT1,OUT2,A0,A1,B0,B1,SEL);
output OUT1,OUT2;
input A0,A1,B0,B1,SEL;
wire A0,A1,B0,B1,SEL;
reg OUT1,OUT2;
always @(A0 or A1 or B0 or B1 or SEL)
begin
OUT1 = (A0 & SEL)|(B0 & ~SEL );
OUT2 = (A1 & SEL)|(B1 & ~SEL );
end
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>1000)$stop;
endmodule
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