odule top;
integer ia0,ia1,ia2,ib0,ib1,ib2,is;
reg a0,a1,a2,b0,b1,b2,s;
wire out1,out2,out3;
mux_behavioral mux1(out1,out2,out3,a0,a1,a2,b0,b1,b2,s);
initial
begin
for (ia0=0; ia0<=1; ia0 = ia0+1)
begin
a0 = ia0;
for (ia1=0; ia1<=1; ia1 = ia1+ 1)
begin
a1 = ia1;
for (ia2=0; ia2<=1; ia2 = ia2+1)
begin
a2 = ia2;
for (ib0=0; ib0<=1; ib0 = ib0+1)
begin
b0 = ib0;
for (ib1=0; ib1<=1; ib1 = ib1+ 1)
begin
b1 = ib1;
for (ib2=0; ib2<=1; ib2 = ib2+ 1)
begin
b2 = ib2;
for (is=0; is<=1; is = is + 1)
begin
s = is;
#20$display("a0=%d a1=%d a2=%d b0=%d b1=%d b2=%d s=%d out1=%d out2=%d out3=%d",a0,a1,a2,b0,b1,b2,s,out1,out2,out3);
end
end
end
end
end
end
end
end
endmodule
module mux_behavioral(OUT1,OUT2,OUT3,A0,A1,A2,B0,B1,B2,SEL);
output OUT1,OUT2,OUT3;
input A0,A1,A2,B0,B1,B2,SEL;
wire A0,A1,A2,B0,B1,B2,SEL;
reg OUT1,OUT2,OUT3;
always @(A0 or A1 or A2 or B0 or B1 or B2 or SEL)
begin
OUT1 = (A0 & SEL)|(B0 & ~SEL );
OUT2 = (A1 & SEL)|(B1 & ~SEL );
OUT3 = (A2 & SEL)|(B2 & ~SEL );
end
endmodule
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